New Year’s Product Development at Cadence, Mentor and Synopsys

With Cadence recently releasing an eUnit test framework with Specman, I figured now would be a good time to suggest a 2014 new year’s resolution for each of the Big 3:

Make functional verification manageable by releasing a SystemVerilog unit test framework with your simulator.

Don’t worry if that sounds complicated because it isn’t. In a couple months, tops, you could have everything you need to package a first release. All it takes is 4 easy steps.

NOTE (to Mentor/Synopsys): Cadence is winning this race so far. If I had to guess, I’d say that their recent additions to Specman mean they’re considering something similar for SystemVerilog if not well into its development. Continue reading Best of 2013

We can’t leave 2013 without a ‘best of’ summary. Here’s the most read 2013 posts for 2013…

Why Agile Will Never Work in Hardware: Of course. This makes complete sense. A post with all the reasons why agile can’t work in hardware was the most popular new entry of 2013.

Time to Blow-up UVM: In this post, I propose an alternative direction to that of UVM; a verification framework with a radical opt-in approach. We’re talking a real platform with (truly) independent pieces as opposed to the hyper-integrated UVM.

Planning to Fail in Hardware Development: This was the first of several posts with analysis of hardware development planning practices based on the 2012 survey I did with Catherine Louis. Lots of interest data here for those who missed it. Worth a look.

You’re Either With Me Or You’re With: The UVM Sequencer: OK… so I tend to pick on UVM a bit. Here’s a post where I talk about some of the unnecessary complexity of UVM sequencer.

How Do Verification Engineers Waste 2 Hours, 52 Minutes, 48 Seconds a Day?: Rounding out the top 5 is analysis of the Mentor Graphics verification survey. (Hint: it has to do with debugging garbage code).

Honorable mention goes to the most read reigning champion of all time (by a mile): Emacs, org-mode, Kanban, Pomodoro… Oh my…. That’s Bryan. He’s an Emacs guys. Please… someone needs to post an entry on kanban with VIM already ;).

Thanks for a successful 2013! Hope we’ll see you back in 2014 for more!


Finally… A Reason For Me to Try Specman

Yes… I know it’s a good tool. People I respect use it and love it. It’s not that I have any specific complaints about Specman, it’s just that I grew up with Vera and SystemVerilog and with the universal support and attention SystemVerilog gets, I’ve never had the urge to try Specman…

…though it seems tool developers at Cadence are trying to change my mind. Continue reading

Unit Testing on Youtube, and DVCon

Started my day with some encouraging observations that I wanted to share…

First, Victor Lyuboslavsky has posted a couple of youtube videos where he covers some of the basics of unit testing and SVUnit. These are good beginner videos that show how easy it is to get started with SVUnit by kicking the tires on You can find the videos on youtube. When you’re done with the videos, you can carry on with this online SVUnit tutorial.

Next, an interesting bit of news for fans of unit testing that use Specman, in Victor’s introductory video he mentions Cadence has added unit test capabilities to Specman appropriately named eUnit. You can see more in their Testing the Testbench webinar that was posted last week. I haven’t seen the video yet (having problems logging into the site) so I’ve seen none of the details. Regardless, it’s encouraging to see one of the big 3 pushing unit testing with a new test framework. (I’ll post a follow-up once I’ve seen the webinar).

Lastly… and yes, it may be a little early for this but I’ll throw it out there anyway… on the DVCon2014 program site I see a paper entitled Applying Test-Driven Development Methods To Design Verification Software In UVM-e from Doug Gibson and Michael Kontz of HP. If you’re planning to take in DVCon, be sure to add that talk to your list.

Happy Monday ;).


Demo SVUnit on

Time to introduce a great new development from an SVUnit early adopter: Victor Lyuboslavsky. Victor is a verification engineer at AMD in Austin that started with SVUnit back in February of 2012. He’s been using SVUnit on and off for almost 2 years now. His most recent work: he’s made it possible for people to build and run SVUnit testcases with no tools or library installation whatsoever. More about that in a second. First, an introduction to his browser-based development tool called EDA Playground.

For the past several months, Victor has been busy developing a browser based development environment called EDA Playground. EDA Playground is interesting because it lets people create a design and testbench, then run simulations with only a web browser. Taken directly from the EDA Playground Overview

Screen Shot 2013-12-11 at 4.25.25 PM

In addition to being able to run simulations in a web browser, EDA Playground offers support for various verification libraries. People can demo small designs built on libraries like UVM, OVM and SVUnit.

Wait… SVUnit? Really?

Yes. Really. To experience SVUnit, all you have to do is go to EDA Playground, load one of the many SVUnit examples, tinker around with the code and hit run! That’s it. No installation, scripting or anything to get started. Just a browser.

Even better is that Victor has loaded an SVUnit tutorial I put together for a verification IP called svunitOnSwitch. Here’s what that looks like…

Screen Shot 2013-12-11 at 3.36.05 PM

If you’ve been meaning to try SVUnit but you haven’t been able to find the time, svunitOnSwitch is for you. It’s the perfect little coding exercise you can develop entirely within EDAPlayground. And of course, you can immediately simulate the results to get a feel for the added rigor and productivity you’ll get with SVUnit. The instructions are there; the code is there; all you need is a browser. Just follow the link to svunitOnSwitch.

Thanks to Victor for the continued support for SVUnit and putting together a useful tool like EDA Playground.