Download the Latest Version of SVUnit from GitHubSVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

SVUnit For Verification Engineers

Verification engineers can use SVUnit to verify testbench components in isolation prior to being used in subsystem or chip/product level testbenches. Because SVUnit imposes very few restrictions on developers, it can be used to develop components for simple Verilog-based testbenches used for directed testing, complex SystemVerilog-based constrained-random testbenches and everything in between. SVUnit also supports development of UVM-based verification testbenches and IP.

SVUnit For Design Engineers

Both verification engineers and the EDA industry as a whole have failed to provide a designer-friendly option for testing RTL. SVUnit changes everything by giving design engineers a practical framework that is easy of use; it does what they need it to do without the unnecessary overhead and baggage of other industry test frameworks. SVUnit gives design engineers a platform for exhaustive stand-alone testing and/or unit testing critical logic prior to release to the verification team, all while avoiding a lot of the overhead required to maintain an ad-hoc testbench. The result is higher quality RTL and an overall decrease in time lost to debug.

Full Documentation and Support

Developers can refer to the SVUnit User Guide to get the most out of SVUnit. Support questions and issues can be filed in the ticket tracker or sent by email to

Shift Right with SVUnit

svunit-tagSVUnit is a highly productive alternative to complex verification methodologies for both design and verification engineers that take pride in delivering high quality, bug-free code. SVUnit has a user base that’s been growing steadily for over 3 years. With support for industry leading simulators including Incisive, Questa, Riviera-PRO and VCS, portability is built-in. A solid code base – unit tested from day 1 – and a long user track record makes SVUnit a low risk, high reward upgrade for any hardware team.

Getting Started with SVUnit

It’s easy to download and use SVUnit. Check out the Getting Started page for more details.

SVUnit User Group Forum

You aren’t the other one using SVUnit! To connect with other users, ask questions and share experience, join the SVUnit User Group. Everyone is welcome!

9 thoughts on “SVUnit

  1. This is great work, Neil! By being a simple stand-alone tool SVUnit imposes few other dependencies on the engineers using it. That doesn’t sound like a big deal but it really is. I see it as being like the dependency management work any good software architect does, only this benefit is in the area of technical tool management.

  2. Whatever happened to SVUnit releases? The download link points to the latest commit. Seems like you’re still bumping the number in RELEASE. I’d much rather work off a tag instead of off a commit.

  3. Hi,
    I changed the “” file in order to launch tests in parallel using fork join, but when I launch my testsuite a test inside an unit test hangs:
    The modified piece of code is as follows:

    print OUTFILE ” task run();\n”;
    print OUTFILE ”;\n”;
    print OUTFILE ” fork\n”;
    foreach $item ( @instance_names ) {
    print OUTFILE ” begin_$item: begin\n”;
    print OUTFILE ” $;\n”;
    print OUTFILE ” end\n”;

    Do you happen to know if we need any adjustment inside the macros to support this?


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