How Do Verification Engineers Waste 2 Hours, 52 Minutes, 48 Seconds a Day?

If you need a good way to waste 36% or your day, debugging code is your best bet!

That’s what I figured Thursday while listening to Harry Foster’s analysis of the 2012 Wilson Research Group Functional Verification Survey commissioned by Mentor Graphics. The survey is meant to show design and functional verification trends from hardware development. It’s well done and well presented by Harry.

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Verifying UVM Error Conditions with SVUnit UVM Report Mock

Verifying error conditions and UVM testbench checkers just got easier! The SVUnit UVM report mock lets you automate testing of UVM errors and fatals to increase confidence that the checkers in your testbench are defect free. The SVUnit UVM report mock is a scoreboard style checker where actual and expected errors are logged and compared to trigger a PASS/FAIL result.

Here’s how it works… Continue reading

Planning to Fail: Long Hours, Mounting Stress and Aggressive Goal Setting

Thus far, we’ve seen numbers related to confidence in project planning and our failure to produce accurate project estimates. In this post, we’ll see that failing to meet project delivery dates doesn’t come from lack of effort, though we will see another sign that we’re indeed setting ourselves up for failure. Here’s three new data points from our project planning survey related to long hours, mounting stress and aggressive goal setting. Continue reading