We see the needs of verification engineers being addressed by frameworks like UVM and techniques like constrained random verification and functional coverage while the needs of designers have been ignored. We wanted to change that, so we created MiniTB.
MiniTB is an open-source responsible development platform (RDP) that design and verification engineers use to create and verify verilog-based designs.
MiniTB is easy to use. After instantiating and connecting a module-under-test, a developer can write and run any number of tests to verify their code. Tests are compiled into a single executable which means little time lost to compilation and fast turnaround. Test status is determined by simple assertions and MiniTB exits with an overall PASS/FAIL summary status. MiniTB supports Cadence Incisive, Mentor Graphics Questa and Synopsys VCS.
If you’re a developer that wants to write better code with MiniTB, take a look at the Getting Started page.
Open-source IP Packaged with MiniTB
2 thoughts on “MiniTB”
Need UVm code basic Environments.
if you’re testing uvm classes, I’d suggest using svunit instead. minitb is geared more toward designer smoke testing whereas svunit has more features (including the uvm hooks) for multi purpose design/testbench unit testing.