Agile IC Methodology From Sonics

Here’s a marketing video posted yesterday from Sonics about an Agile IC Methodology they’re promoting in the run-up to ARM TechCon. Normally I might not post stuff like this directly on but I’m making an exception because one of the people in the video is me… along with some other guys that are far more recognizable 🙂 .

If you watch the video, I hope you’ll take a few minutes to comment. I’m interested to hear what people think about it and the fact that a few different folks within the industry are coming together to promote agile development.

[youtube_sc url=9xVfIqcY1Qw width=640 height=480]


Now What?

You’ve started doing TDD or unit testing your systemverilog code with SVUnit, your defect rate is down and you’re producing better code. You’re at the point where your experience could benefit the rest of your team but you’re not sure how to get the point across.

What do you do? Continue reading

Stepping Through an RTL Unit Test

Pretty much every testbench I’ve ever built, used or seen has a free-running clock that’s driven within a while or forever loop. Not much can happen without the clock in a synchronous design so defining the clock logic is usually the first and most obvious thing we do as verification engineers.

Screen Shot 2014-09-22 at 1.51.14 PM

Assuming your design-under-test is synchronous to the positive edge (they almost always are), testbench components usually do their work somewhere off the posedge to avoid races. With even a simple testbench these days, there will be several components, each with their own thread, pushing or pulling data from various interfaces on the DUT. The free-running clock is that steady bass drum beat that holds everything together. Continue reading

TDD for Design Proof-of-Concept

It’s finally time to see if TDD is a viable technique for writing RTL with verilog. But first, a little backstory…

For the Agile2014 conference in Orlando this past summer, Soheil and I built an Agile hardware/software co-development demo using a Xilinx FPGA with an ARM dual core Cortex-A9 to show how TDD could be used to write embedded software, drivers and RTL (i.e. TDD of a complete system). Continue reading

Agile Hardware Hangout Schedule

I’ve scheduled a regular agile hardware hangout to run weekly on Wednesday nights. You can either join us from the google group where I’ll post links and updates or you can go directly to the google hangout every wednesday at 7:30pst. Anyone interested in agile hardware development can join to ask questions and/or talk about whatever they like. Hope to see you there!