SVUnit v1.1 – Improved Module/RTL Support

Today, I posted a new v1.1 release of SVUnit on GitHub. The “new” feature in version 1.1 is a refactored/simplified framework meant to increase usability, especially for people that want to do TDD or unit testing of RTL.

Screen Shot 2013-04-25 at 10.48.28 PMUp until now, I think SVUnit has been pretty decent for building systemverilog class and interface based verification IP because the class based structure of the framework was originally intended to support classes and interfaces. Modules though… not so much… so while class/interface support was a strength, module support – and consequently support for design IP – was a significant weakness. The intention of v1.1 is greater support for modules by changing to a module-based structure.

In v1.1, the unit test template is like a mini-testbench. There’s an instance of the UUT in the mini-testbench. The constructor from past releases that we used to create and connect any peripheral functionality has been replaced by a build() function that’s automatically called by the testsuite prior to anything else happening. There’s the same setup and teardown methods with a minor change then the test macros are the same as what was there. In terms of how tests are run and the sequence of events that are followed, nothing really changes.

I’ll be writing more about it in the next few weeks as I continue to simplify the code base. In the meantime, I’ve embedded a condensed dump of the unit test template created by create_unit_test.pl (condensed in that I’ve removed some of the comments and whitespace so it fits on my screen).

If you’ve got comments on the format relative to prior versions, I’d appreciate you posting them. If this is cleaner and more usable, I’d like to hear it. If not, of course I’d prefer to hear that, too :).

-neil

 

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