In a post a couple weeks ago called Sorry Design Engineers, I Can Do Better, I told design engineers that I’d do a better job of giving them what they need to unit test their RTL. I felt like I’ve been neglecting design engineers and decided I needed to set a new, more inclusive course. Tonight I took a first step in that direction. I’ve released SVUnit 3.10 with a simple clock and reset utility that’ll make it easier for design engineers to unit test synchronous and asynchronous logic. I also recorded a 25min code demo for design engineers to show how they can use SVUnit to unit test RTL modules. Continue reading
I’m looking for a list of discussion topics for a panel discussion that’ll happen at DAC in June. It’ll be a very informal/interactive session. We’ll take a list of topics and cycle through them in a series of 5-10min discussions. Audience will be encouraged to participate; agreeing or disagreeing as they see fit.
I’m looking for topics to get discussion rolling and am hoping you’ll chime in with your ideas. So if you’ve got a few minutes, I’d appreciate you joining the google group discussion and dropping a few comments or questions regarding unit testing, test driven development, SVUnit and/or related. As many as you can think of. Topics could be for or against unit testing, doesn’t matter. In fact the tougher the topic, the better! I’ll take 10-15 and and quote them in a series of slides. We’ll show the slides and invite the audience to weigh in.
Thanks for helping out!
Advanced verification methods put chip leads and managers at a real disadvantage, especially when it comes to visibility and predictability. With long testbench development times, early progress in constrained random is essentially based on trust; being random, the inherent uncertainty makes predictable scheduling and release milestones rare. Continue reading
There were a lot of highlights from DVCon when it comes to SVUnit. In fact, it was the most successful three day stretch I’ve had in a very long time. From verification engineers in particular, it was the first time I had the feeling that SVUnit is gaining genuine acceptance. The stories and experience I’m finding in people are fantastic. Interest and usage is growing. Everything is awesome…
…kind of. Continue reading
One suggestion that came out of the SVUnit User Group Lunch last week during DVCon was a mailing list so that SVUnit users could keep in touch with questions, etc. Sounded good to me so I’ve set up an SVUnit User Group. It’s a google group. Anyone can join.
With the lunch being a great first step (for me it felt like a giant leap) in building a real community around SVUnit, my hope is that this is the natural next step giving us users an online home to congregate and support each other.
If you’re an SVUnit expert, someone entirely new to SVUnit or anyone in between, I hope you’ll join us in the SVUnit User Group to share your questions and experience!
The last 2 days at DVCon have been about the best possible for SVUnit. Maybe even better than that.
First was the poster sessions on Tuesday just before lunch. Josh Rensch and I had a paper called Do You Verify Your Verification Components. Being that this was my first time to DVCon, I had no idea how the turn out would be and/or whether or not people would be interested enough in the paper to stop and discuss it. To be honest, I had prepared myself to just stand there for 90min while people walked by. Thankfully that didn’t happen.
Even though it was a paper about testing testbench IP that talked about TDD and SVUnit – none of which are remotely close to being mainstream ideas – people were actually interested. Lots of questions, lots of great discussion and I got the feeling there was actual acceptance which was a tad surreal. Credit goes to Josh for taking the lead on writing the paper and putting together the poster. He did most of the work. I was in the car on my way back to the hotel when I got a text from him saying we got a 3rd place award for the paper. Pretty cool.
That was Tuesday. The highlight from Wednesday was the SVUnit User Group Lunch. Full disclosure: I was nervous about this from the moment we started planning it. Never before attempted by me. I wasn’t sure people would show up. That and I doubted we would have enough to talk about. Happy to say, though, that the lunch went better than I could have hoped. Way better.
We had 18 people in total, which is about a dozen more than I thought was possible. There was a perfect mix of experts, soon-to-be-experts, people who’ve been interested in SVUnit but haven’t had a chance to get started and others who didn’t really know much about it. I did my best to get the discussion rolling and then everyone else just kind of took over. It was ideal.
Thanks to everyone that came to the lunch, spoke up, asked questions, chimed in with opinions, signed the SVUnit banner and posed for a picture (extra thanks to my colleague Rich DesMarais for organizing). It was a pretty special day. I felt like this was a big step in building a community around SVUnit. Hopefully, it’s the first of many!
An Introduction to Unit Testing with SVUnit is a 5 part video course. It starts with my opinions on how advanced verification methods have failed to reach their potential, goes on to introduce SVUnit with a couple of coding examples and finishes with data from case studies that show the value of unit testing with SVUnit.
While the course is meant to flow naturally beginning to end, each of the 5 parts stands well on its own. Depending on what you’re after, here’s a little guidance on what sessions and details are best for you… Continue reading
Version 3.8 of SVUnit, just released, improves support and usability for people unit testing UVM components.
XtremeEDA, are responsible for adding and testing the version 3.8 features. That makes Colleen and Dave the newest active contributors to SVUnit!But before we talk about new features, I want to mention that the cool part of this release… for me anyway… is that I didn’t have to do anything! Colleen Piercey and Dave Read, colleagues of mine from
As far as new 3.8 features, people can now use create_unit_test.pl to generate a UVM specific test case template. The template gives test writers placeholders for connectivity in an auto-generated UUT wrapper. It also inserts file includes, package imports and required function calls in the setup and teardown to avoid people having to do it themselves. Importantly, the new UVM test case template compiles and runs with UVM as-generated so you start writing tests from a known good state. Continue reading
The inaugural SVUnit User Group Lunch will take place the week of DVCon in San Jose. Bringing SVUnit users together is something I’ve wanted to do for a while. So much so that I’ve held off using the word ‘inaugural’ for my entire life, saving it for exactly this moment!
Details are still being worked out, but so far it’s looking like lunch time, Wednesday March 2, somewhere near the Doubletree Hotel in San Jose. It’ll be an informal gathering where developers that are either using, evaluating or thinking of using SVUnit can get together, get to know each other and share experience and opinions. We’ll have room for about a dozen people (happy to say I’ve got 3 confirmed already).
This is an important community building exercise that I’m pretty excited about. With the SVUnit user base growing, now seems like the right time to start learning from each other. If you’re an SVUnit user and/or you want to meet other SVUnit users over lunch, please let me know at: email@example.com. I’ll follow-up with details as they get sorted out.
I think we have two fairly critical barriers to overcome before agile hardware gets any serious traction from semiconductor teams. Continue reading