Verilog/VHDL Mixed Language Unit Testing

 

SVUnit supports mixed language Verilog/VHDL unit testing.

Finally.

Download the Latest Version of SVUnit from GitHubIt didn’t take much to do it but for some reason it took me a loooooooong time to get at it. It involves a new switch to the runSVUnit command line. Users can now specify a ‘-m <vhdl file list>’ where vhdl file list is all their VHDL files and extra VHDL-related command line switches. It’s been tested with Modelsim and Incisive. Probably works with VCS though I can’t say for sure because I haven’t seen it with my own eyes. If someone wanted to give VCS a try and let me know what happens, I’d appreciate it!

The updated runSVUnit usage is (emphasis on -m|–mixedsim <vhdlfile>):

screen-shot-2016-09-14-at-9-01-56-pm

As an example, if you’re unit testing a mixed language design with Modelsim where VHDL files in your design are listed in myVHDL.f and your Verilog files are in myVerilog.f, your command line would be…

runSVUnit -s modelsim -m myVHDL.f -f myVerilog.f

As always, if there’s any trouble with it you can log an issue on github, send me an email at neil.johnson@agilesoc.com or leave something in the comments. If you were waiting on mixed language support to get started with SVUnit, now is your chance. Just scroll up and hit the big blue button to get started!

Happy unit testing!

-neil

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