Advanced verification methods put chip leads and managers at a real disadvantage, especially when it comes to visibility and predictability. With long testbench development times, early progress in constrained random is essentially based on trust; being random, the inherent uncertainty makes predictable scheduling and release milestones rare.
SVUnit, in part, is meant to address the relative absence of visibility and predictability in verification which is why I’m hoping chip leads and managers will tune into the Introduction to Unit Testing with SVUnit course on Verification Academy. Not the whole course, just the 3 parts that can help quantify the problem, introduce SVUnit and summarize the benefits. That’s about 20 minutes total and well worth your time.
A description of the problems we create with advanced verification methods is what you’ll find in part 1. It goes through 4 characteristics of late delivery, spelling out the difficulty in making and delivering on promises using constrained random verification.
Initial code quality is the kicker for us when it comes to late delivery; part 2 is where SVUnit is introduced as being part of the solution. It’s open-source, easy to use, supports all leading simulators, fully supported with user guides and examples and there’s a community of users ready to help.
The benefits of unit testing with SVUnit are spelled out in part 5. There are a couple of case studies for reference. Also endorsements from teams that use SVUnit.
All said, I think it’s important to put forward ideas and techniques that can help fill gaps that advanced verification methods have yet to fill. That’s the intent with SVUnit. It’s a simple Verilog test framework for improving code quality. It’s also a tool that improves visibility and predictability, issues that are critical for chip leads and managers. The Introduction to Unit Testing with SVUnit course should be enough to get you started with improvements to all the above!