Simple Clock and Reset Support in SVUnit

Screen Shot 2016-04-28 at 8.54.17 AMIn a post a couple weeks ago called Sorry Design Engineers, I Can Do Better, I told design engineers that I’d do a better job of giving them what they need to unit test their RTL. I felt like I’ve been neglecting design engineers and decided I needed to set a new, more inclusive course. Tonight I took a first step in that direction. I’ve released SVUnit 3.10 with a simple clock and reset utility that’ll make it easier for design engineers to unit test synchronous and asynchronous logic. I also recorded a 25min code demo for design engineers to show how they can use SVUnit to unit test RTL modules.

The clock and reset utility is found in the release package under svunit_base/util/clk_and_reset.svh. In there you’ll find a macro called `CLK_RESET_FIXTURE(…). The macro is used to declare clk and reset regs that can be connected to an RTL unit under test. There are also functions for reset, advancing the clock and moving to valid sample points beyond the clk edge.


This is a macro that declares the clk and rst_n regs as well as the tasks to control them. This is a parameterized macro where the first argument is the half period of the clock (in time units) and the second argument is the reset length measured in clock cycles. The macro should be used inside unit test templates; the clk and rst_n regs should be connected to UUT clock and reset inputs.

task reset()

Assert the active low rst_n for RESET_LENGTH cycles then deassert.

task step(int n = 1)

Advance the clk n cycles. The default is to step 1 clock cycle.

task nextSamplePoint()

Advance simulation time beyond the current clock edge – if you are on a positive clock edge – to avoid race conditions when sampling synchronous UUT outputs.

task pause()

Insert a #0 delay to avoid race conditions when sampling asynchronous UUT outputs.

Getting acquainted with the new clock and reset utilities can be done in 1 of 2 ways. First, you could take a look at the newest SVUnit example in the download package at $SVUNIT_INSTALL/examples/modules/clk_and_reset. There’s a design example in there with unit tests for synchronous and asynchronous IO. It’s simple, but I think it’s a good start in that it’ll help designers over a few common hurdles.

Another way to see the clock and reset utilities in action is to watch the newest SVUnit 101 for RTL AgileSoC-on-demand video. In that, I go through the clk_and_reset example from the ground up; starting with a new unit test template, instantiating and connecting the RTL, writing tests, connecting the CLK_RESET_FIXTURE and all.

There’s lots more possible for design engineers that want to use SVUnit. But this is the all important first step.


Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.