So I’ve been waiting for about 5 years now for someone to turn our AgileSoC logo into a shirt and send it to me without me asking. 5 Years!
Ok… not entirely true. I haven’t been waiting for an AgileSoC shirt but much to my surprise, it’s happened anyway! Thanks to Matt Plavcan devoting his spare time to something fully and completely awesome, I have a new AgileSoC shirt.
Officially… in case it’s not obvious… this is my new favorite shirt. Besides the shirt, Matt also sent me a few DIY iron-ons with various logo configurations. All that for the low, low price of 2 beers.
No solid plans for more shirts yet though it would be awfully selfish of me to keep them for myself. I’m thinking I might pay this forward to some agile hardware developer that does something special for the community. So go do something good… and keep an eye on your mailbox. Someone sending me an AgileSoC shirt totally out of the blue means pretty much anything can happen :).
SNUG Silicon Valley is all wrapped up for another year. I think my talk on tuesday morning went pretty well. Finding the right angle for introducing agile hardware practices has been a real trick for me and this week I felt I took a step forward. For technical practices, TDD is still my goal. For the hardware crowd it seems my UVM-UTest talk focusing on unit testing could be the right path for getting there.
(If you weren’t at SNUG and you have a group that’d be interested in How UVM Makes The Case For Unit Testing, let me know at firstname.lastname@example.org. I’m always happy to repeat past presentations in person or via webex!) Continue reading →
Time for another UVM challenge…
So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll be up on stage talking about UVM-UTest and how UVM makes the case for unit testing. Aside from the talk and the paper, I’ve also been pondering other ways to get the point across that unit testing is an effective way to verify hardware. I’ve been having trouble thinking of something appropriate… until tonight… I think… I hope… Continue reading →
Next week is SNUG in San Jose and I’m looking forward to it. I’ll be presenting How UVM Makes the Case For Unit Testing in the Verification I track from 10:30-12 on Tuesday morning and would love to see some AgileSoC followers sit in. Here’s a snapshot of the abstract from the SNUG website.
Continue reading →
I always find the aftermath of DVCon interesting. I’ve never been to the conference but it always seems to be well covered. Between people live tweeting different sessions and others blogging, it always feels like I can be near there without being there.
The panel session that caught my eye this year was about something called the verification gap. In an article posted last week called Pointing Fingers in Verification, Brian Bailey made it sound like EDA representatives and users were doing their best to defer responsibility and deflect criticism when it comes to creating and closing the verification gap (it’s a good article… you should go read it when you’re done here).
I like these discussions so I’d like to add my 2 cents :). Continue reading →
Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was cool and verification was where junior engineers started. Constrained random verification hadn’t hit the mainstream. There wasn’t much functional coverage to speak of. I think Specman and Vera were around but the user-base was relatively small. There was no Systemverilog and there was no UVM. Basically, we were back in the stone age of directed testing. Any knucklehead could do it. Thankfully, I was perfectly qualified. Continue reading →
I’ve gone through an overhaul of the SVUnit scripting. Specifically, the makefiles are out and a simpler build/run script is in. Most of what’s under the hood is the same (i.e. the construction of the systemverilog code framework). In short, create_svunit.pl + makefiles are out; runSVUnit is in.
Here’s a dump of the runSVUnit usage. Still subject to change so if you see something you don’t like or you don’t see something you would like, now is the time to bring it up :).
Some additional notes… Continue reading →
After some back-and-forth with SVUnit users over the last several months, I reckon it’s finally time to get rid of the make user interface. Turns out, the incremental construction of the framework that make helped with isn’t all that necessary. It also seems some hardware developers get a little nervous around makefiles (admittedly, they make me nervous at times). In response, I’ll be putting together a simpler build/run script in place of what’s there now.
If you’re in favour of a new scripting interface and would like to help out by critiquing a first release, please let me know at email@example.com.
I have unit tests for the scripting to rely on for quality so what I end up with should be pretty solid. Still, it’d be nice for me to get a few opinions before I release it.