Agile2014 Demo – Weeks 2 and 3

Now is probably the right time to start talking about the board we’re using for our agile SW/HW co-development demo… or I should say hope to be using considering it’s currently on backorder (we’re expecting a mid-June delivery).

It’s called a Zedboard (we borrowed the picture from Like most development kits, it’s got a lot of stuff on it, much of which we won’t be touching at all. What we definitely will be using is the Xilinx Zynq programmable SoC in the middle. It’s the small’ish Z-7020 device with an ARM dual-core Cortex-A9. The other important part for us is the HDMI connector. The plan of record is to run our Conway’s Game of Life application on the A9 while the visuals are sent to a monitor via the HDMI.

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Agile2014 Demo – Week 1

Today will be 3 weeks of development on our Agile SW/HW Co-development demo. This is a recap of week 1. Week 2 to follow and then we’re all caught up!

We’ve decided on an application. We wanted something simple, visual, fun and familiar so that people at the Agile2014 conference would feel comfortable sitting down and giving it a try. To that end, we figured Conway’s Game of Life would fit the bill. If you’re not familiar with Conway’s Game of Life, here’s a screenshot from the opening of its wikipedia pageContinue reading

SVUnit Adds Support For Aldec Riviera-PRO

Download the Latest Version of SVUnit from GitHubHere’s something to get Aldec users excited: SVUnit now supports Riviera-PRO. That means it’s no longer just Mentor Graphics, Cadence and Synopsys users that have the option of unit testing high quality Systemverilog RTL and testbench code, Aldec users can now join in the fun!

For Riviera-PRO support, you’ll want v2.8 from GitHub. Fastest way to download it is to hit the big blue button to the right. From there, I’d follow the instructions in the README to start building your own short demo. That should take about 10min (if it takes longer than that, it’s probably my fault… not yours… so feel free to send me a nastygram with any troubles you’re having). Perusing the examples directory is a good second step. The designs in there should work just as they do with any of the other simulators. For further instructions, you can take a look at the SVUnit page or search for past blog posts tagged with SVUnit. Continue reading

Yes… This is an AgileSoC Shirt

photo 2So I’ve been waiting for about 5 years now for someone to turn our AgileSoC logo into a shirt and send it to me without me asking. 5 Years!

Ok… not entirely true. I haven’t been waiting for an AgileSoC shirt but much to my surprise, it’s happened anyway! Thanks to Matt Plavcan devoting his spare time to something fully and completely awesome, I have a new AgileSoC shirt.

Super. Duper!

Officially… in case it’s not obvious… this is my new favorite shirt. Besides the shirt, Matt also sent me a few DIY iron-ons with various logo configurations. All that for the low, low price of 2 beers.

No solid plans for more shirts yet though it would be awfully selfish of me to keep them for myself. I’m thinking I might pay this forward to some agile hardware developer that does something special for the community. So go do something good… and keep an eye on your mailbox. Someone sending me an AgileSoC shirt totally out of the blue means pretty much anything can happen :).


SNUG Unit Testing Finale

2014-03-24 14.53.48SNUG Silicon Valley is all wrapped up for another year. I think my talk on tuesday morning went pretty well. Finding the right angle for introducing agile hardware practices has been a real trick for me and this week I felt I took a step forward. For technical practices, TDD is still my goal. For the hardware crowd it seems my UVM-UTest talk focusing on unit testing could be the right path for getting there.

(If you weren’t at SNUG and you have a group that’d be interested in How UVM Makes The Case For Unit Testing, let me know at I’m always happy to repeat past presentations in person or via webex!) Continue reading

UVM-UTest File-a-Bug Challenge at SNUG

Time for another UVM challenge…

So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll be up on stage talking about UVM-UTest and how UVM makes the case for unit testing. Aside from the talk and the paper, I’ve also been pondering other ways to get the point across that unit testing is an effective way to verify hardware. I’ve been having trouble thinking of something appropriate… until tonight… I think… I hope… Continue reading

Forget About the Verification Gap

I always find the aftermath of DVCon interesting. I’ve never been to the conference but it always seems to be well covered. Between people live tweeting different sessions and others blogging, it always feels like I can be near there without being there.

The panel session that caught my eye this year was about something called the verification gap. In an article posted last week called Pointing Fingers in Verification, Brian Bailey made it sound like EDA representatives and users were doing their best to defer responsibility and deflect criticism when it comes to creating and closing the verification gap (it’s a good article… you should go read it when you’re done here).

I like these discussions so I’d like to add my 2 cents :). Continue reading

You’re Either With Me Or You’re With: The UVM Register Package

Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was cool and verification was where junior engineers started. Constrained random verification hadn’t hit the mainstream. There wasn’t much functional coverage to speak of. I think Specman and Vera were around but the user-base was relatively small. There was no Systemverilog and there was no UVM. Basically, we were back in the stone age of directed testing. Any knucklehead could do it. Thankfully, I was perfectly qualified. Continue reading