Slacking off? Me?? I guess maybe I have been because someone finally got sick of waiting for me to get to a new SVUnit feature and added it themselves…
…and that made me happy.
As of 2 about weeks ago, Tudor Timisescu is the latest addition to the list of active SVUnit developers-at-large. That brings us to a grand total of 1… which is 1 more than the 0 we had before! Continue reading
I just posted version 3.1 of SVUnit to GitHub. If you’ve been waiting patiently for me to get rid of the makefiles, the wait is over. From here on, we’ve got a simple command line script to run SVUnit unit tests with any of IUS, Questa, Modelsim, Riviera PRO and VCS.
The best place to start with version 3.1 is the README.txt in the release package. Pay attention to step 5 because that’s where everything changes (for the simpler and better). All the code in the release package, including the examples, has been updated to match the new scripts so there shouldn’t be anything misleading in there. Also exciting is that all the documentation has been removed (it was incredibly out-of-date and misleading to say the least). I still need to update the SVUnit on demand videos which I’ll do as soon as I can.
Lastly, here’s the usage for the new run script that I’ve been touching up over the past several weeks…
If you spot anything that needs attention, I’d appreciate it if you could file a ticket. Touch-ups should be easy to turn around quickly. FYI… the next updates I’m considering are support for UVM1.2 and parameterized unit test classes as well as a few other things people have been asking for.
Thanks to those that gave feedback and helped get us to version 3.1!
I’ve had people asking about the SVUnit new scripting proposal I posted a few months back. I forgot about it for a while but now I’m back. I’ve taken some of the feedback I’ve received and folded it into a new version. Slightly different in that I’ve added switches for compile and runtime options.
Here’s the help. Take a look and let me know what you think…
This is ready to go. I have a couple people trying it out. If you’d be willing to test-drive the new scripts before an official release, I’d sure appreciate it. Just let me know at email@example.com and I’ll ship you a copy. If all goes well, I’d expect to release this within a month or so as version 3.0.
Thanks in advance for you comments!
Last week I stumbled across a verification post that used my favorite verification graphic from the Wilson Research Group Functional Verification Survey that Mentor sponsors every few years. Here it is again for anyone that hasn’t seen it posted here before (I’m sure this makes about a half-dozen times for me. It is, after all, my favorite verification graphic)… Continue reading
Here’s something to get Aldec users excited: SVUnit now supports Riviera-PRO. That means it’s no longer just Mentor Graphics, Cadence and Synopsys users that have the option of unit testing high quality Systemverilog RTL and testbench code, Aldec users can now join in the fun!
For Riviera-PRO support, you’ll want v2.8 from GitHub. Fastest way to download it is to hit the big blue button to the right. From there, I’d follow the instructions in the README to start building your own short demo. That should take about 10min (if it takes longer than that, it’s probably my fault… not yours… so feel free to send me a nastygram with any troubles you’re having). Perusing the examples directory is a good second step. The designs in there should work just as they do with any of the other simulators. For further instructions, you can take a look at the SVUnit page or search for past blog posts tagged with SVUnit. Continue reading
SNUG Silicon Valley is all wrapped up for another year. I think my talk on tuesday morning went pretty well. Finding the right angle for introducing agile hardware practices has been a real trick for me and this week I felt I took a step forward. For technical practices, TDD is still my goal. For the hardware crowd it seems my UVM-UTest talk focusing on unit testing could be the right path for getting there.
(If you weren’t at SNUG and you have a group that’d be interested in How UVM Makes The Case For Unit Testing, let me know at firstname.lastname@example.org. I’m always happy to repeat past presentations in person or via webex!) Continue reading
Time for another UVM challenge…
So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll be up on stage talking about UVM-UTest and how UVM makes the case for unit testing. Aside from the talk and the paper, I’ve also been pondering other ways to get the point across that unit testing is an effective way to verify hardware. I’ve been having trouble thinking of something appropriate… until tonight… I think… I hope… Continue reading
Next week is SNUG in San Jose and I’m looking forward to it. I’ll be presenting How UVM Makes the Case For Unit Testing in the Verification I track from 10:30-12 on Tuesday morning and would love to see some AgileSoC followers sit in. Here’s a snapshot of the abstract from the SNUG website.
I always find the aftermath of DVCon interesting. I’ve never been to the conference but it always seems to be well covered. Between people live tweeting different sessions and others blogging, it always feels like I can be near there without being there.
The panel session that caught my eye this year was about something called the verification gap. In an article posted last week called Pointing Fingers in Verification, Brian Bailey made it sound like EDA representatives and users were doing their best to defer responsibility and deflect criticism when it comes to creating and closing the verification gap (it’s a good article… you should go read it when you’re done here).
I like these discussions so I’d like to add my 2 cents :). Continue reading
Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was cool and verification was where junior engineers started. Constrained random verification hadn’t hit the mainstream. There wasn’t much functional coverage to speak of. I think Specman and Vera were around but the user-base was relatively small. There was no Systemverilog and there was no UVM. Basically, we were back in the stone age of directed testing. Any knucklehead could do it. Thankfully, I was perfectly qualified. Continue reading